1. Field of the Invention
This invention relates to a computer system with an expansion unit, and especially to controlling both a DMA transfer and a normal transfer between the expansion unit and a computer body.
2. Description of the Related Art
Conventionally, although ISA (Industry Standard Architecture) and EISA (Extended ISA) buses are conventional system buses used in personal computers, recently a PCI (Peripheral Component Interconnect) bus has been employed in desktop type personal computers to increase the speed of data transfer and organize system architecture, independently of the kind of processor.
In a PCI bus, block transfer is the basis of substantially all data transfer. Transfer of each block is effected by burst transmission. For example, a maximum data transfer speed of 133 megabytes/sec. is effected, when the data bus has a width of 32 bits.
Therefore, when a PCI bus is used, data transfer between I/O devices and between a system memory and an I/O device is executed at high speed, so that system performance is increased.
The PCI bus has not only been applied in desktop type personal computers, but also in portable personal computers such as notebook types.
In desktop type personal computers, option cards for function expansion such as ICES PCI expansion cards and ISA expansion cards are directly mounted in an expansion slot on the system board. In such cases, a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines corresponding to a plurality of types of DMA channels are defined for each ISA expansion slot to which an ISA expansion card is connected (one pair of lines per slot). As a result, because each ISA expansion card uses a specific DMA channel such as one combination of DREQ and DACK# corresponding to that card, the DMA transfer function of a DMAC (direct memory access controller) core on the system board is utilized.
Consequently, in a desktop type personal computer, devices which do not require a DMAC such as PCI bus masters etc., and devices which do require a DMAC such as ISA devices etc., are easily mixed.
However, even in portable personal computers, it is necessary to mount option cards such as PCI expansion cards and ISA expansion cards via an expansion unit known as a desk station. In such a case, it is necessary to reduce as much as possible the number of signal lines leading out from the portable personal computer to the desk station. This is because if the number of signal lines leading out to the desk station is increased, this leads to an increase in the number of pins of the LSI circuit mounted on the system board for interfacing with the desk station. Further, this leads to an increase in the number of pins of the connector for connecting the portable personal computer and the desk station. These increases in turn result in an increase in the cost of the portable personal computer and reduction of system mounting efficiency.
As a result, there are not provided a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines leading out to the desk station. However, if control lines for DMA transfer are not provided to the desk station, option cards such as ISA cards cannot utilize DMA transfer.
Recently, a protocol for transmitting and receiving DMA request signals (DREQ) and DMA acknowledgment (DACK#) signals between an ISA expansion card installed in the desk station and a MAC core on the system board, without using a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines, has been considered.
This protocol uses a pair of signals consisting of a bus access request signal (REQ#) and a bus access enable signal (GNT#) on a PCI bus. Under this protocol, DMA requests (DREQ) of a plurality of channels are transferred from the ISA expansion card of the desk station to the MAC core connected to the PCI bus by means of a serial transfer for DMA request signals (DREQ) and a bus access request signal (REQ#). Also, DACK# are transferred from the MAC core to the ISA expansion card of the desk station by means of serial transfer for DMA acknowledgment (DACK#) and a bus access enable signal (GNT#) indicating access to the bus has been granted. Hereafter, REQ# and GNT# used for a serial transfer of DREQ and DACK# are designated serial REQ# and serial GNT#.
By providing a PCI-ISA bridge interface in the desk station, the DMA serial channel protocol which serially transfers a plurality of DMA channels in this way needs only signal lines corresponding to a PCI bus leading out to the desk station. Therefore, it is possible to use both PCI expansion cards and ISA expansion cards.
However, the PCI-ISA bridge within the desk station needs a process for serializing DMA request signals (DREQ) of a plurality of channels and a process for serial-to-parallel converting DREQ channel information provided by a serial transfer from the DMAC core and imposes DMA within the DMAC core, with regard to notification of DMA request signals (DREQ). Therefore, substantial time is required from generation of a DMA request signal (DREQ) from the ISA expansion card to reception of the DMA request signal by the DMAC core.
Moreover the PCI-ISA bridge needs a process for serializing DACK# of a plurality of channels at the DMAC core end and a process for serial-to-parallel converting DACK# channel information provided by a serial transfer and a process for returning to the original DACK#, with regard to the serialized DACK#. Therefore such notification takes substantial time.
When transmission and reception of DREQ and DACK# by using the DMA serial channel protocol takes substantial time, a misoperation can occur. A mechanism of this misoperation is explained with reference to FIG. 1 and FIG. 2.
FIG. 1 shows a system block diagram of a conventional portable computer which utilizes a DMA serial channel protocol. FIG. 2 shows the sequence of a conventional DMA serial channel protocol in such a portable computer.
As shown in FIG. 1, a host-PCI bridge device 102 is provided between a CPU 101 and an internal PCI bus 104, whereby the processor bus of the CPU and the internal PCI bus are connected. A system memory 103 is controlled by the host-PCI bridge device 102. Also, a DMAC core 105 is connected to the internal PCI bus 104. The internal PCI bus 104 and a desk station DS 110 are connected by a PCI-DS bridge device 106. A DS-PCI/ISA bridge device 107 is provided inside the desk station DS 110. An external PCI bus 108 and an external ISA bus 109 are connected to the DS-PCI/ISA bridge device 107.
In this system, transmission and reception of DREQ and DACK# between ISA expansion cards A and B on the external ISA bus and the DMAC core 105 on the internal PCI bus are performed as illustrated in FIG. 2, according to the following DMA serial channel protocol.
(1) The ISA expansion card A generates a DREQ A active.
(2) The DS-PCI/ISA bridge device 107 performs serial transfer by utilizing a REQ#, and transmits the DREQ A to the DMAC core. In this case, a number of serial bit strings from a start bit S of the serial REQ# indicate that the DMA channel A is active.
(3) The DMAC core receives the serial REQ# and generates an internal DREQ A (Int. DREQ A) corresponding to the DMA channel (channel A) specified by the serial bit strings. The Int. DREQ A is supplied to one DREQ input port of a plurality of channels within the DMAC core.
(4) The DMAC core performs a serial transfer by utilizing a GNT# and transmits a DACK A# corresponding to the DREQ A. In this case, the DMA channel (channel A), by which DMA transfer is executed, is selected by bits strings following the start bit S of the serial GNT#.
(5) The DS-PCI/ISA bridge device 107 receives the serial GNT# and generates a DACK A# corresponding to the DMA channel specified by the bit strings. The ISA expansion card A is notified by the DACK A# of the commencement of DMA transfer utilizing the DMA channel A.
Within such a sequence, during the period from (2) to (4), it is possible for the DS-PCI/ISA bridge device to retransmit the serial REQ#. The trigger for this retransmission is at the point when the DREQ B from the ISA expansion card B is changed to an active state.
In such a case, in order to retransmit a serial REQ# for notification that DREQ A and DREQ B are generated respectively from the two ISA expansion cards A and B, the REQ# being generated are temporarily inactive. At that time, the DMAC core erroneously judges this as being the ISA expansion card A rendering the DREQ A inactive. There is the danger that, in response, the DMA core renders the internal DREQ A inactive, As a result, the DMAC judges that DMA transfer corresponding to the ISA expansion card A was concluded. Therefore, a timing in which the DACK A# disappears results. In such a case, the DMA transfer of the ISA expansion card A finishes in an illegal state.
Further, although not shown in FIG. 2, in the period of sequence (5), if retransmission of the serial REQ# arising from generation of a DREQ B from the ISA expansion card B is performed, similarly, DMA transfer to the ISA expansion card A is interrupted.
If DMA serial channel protocol is performed in this way, notification of the state of the latest DREQ of each I/O device by one REQ# line is required. Therefore, there is a danger that the above-described problem occurs in the transfer protocols of DREQ and DACK#, with a resulting misoperation of the DMA transfer.
In addition, the DS-PCI/ISA bridge device 107 requires switching of bus direction (direction of address and control bus), according to the location in which the bus master corresponding to the DMA transfer is executed. However, in a portable computer system utilizing serial channel protocol, the timing at which this bus direction is switched is delayed. As a result, the time until execution of DMA transfer may be undesirably long.
More particularly, after the DMA transfer is ready to proceed, bus cycles generated on a PCI bus differ greatly according to whether the I/O device for which execution of DMA transfer is specified by serial transfer of the DACK# is an ISA bus master or not. Namely, the bus cycles are executed by the ISA bus master in the case in which a DACK# is sent back to an ISA bus master connected to the external ISA bus. If an ISA bus master is not connected to the external ISA bus, all bus cycles are executed by the DMAC core. As a result, a required bus direction depends on whether the I/O device is an ISA bus master or not.
Therefore, the DS-PCI/ISA bridge device 107 cannot determine whether an I/O device for which DMA transfer execution is specified is an ISA bus master or not, up to the time when a master signal MASTER# on the external ISA bus is changed. As a result, the bus direction switching timing is delayed and it takes substantial time until execution of DMA transfer commences.